一种低功耗LDO线性稳压器的设计

A Low Power LDO Linear Regulator Design

基于UMC40nm工艺,设计了一种为数字电路供电的LDO线性稳压器,输出电压为1.1V。该电路工作在大负载电流和小负载电流两种模式下。对LDO的基本原理进行了分析,详述了关键电路的设计,最后通过cadence spectre仿真验证了设计的可行性。低功耗模式下,静态电流可以低至3.75uA。全负载范围内,增益可达60dB以上,电源抑制比轻载时可达-52dB,重载时可达-62dB。

Based on the UMC 40nm process,an LDO linear regulator for powering digital circuits is designed,with an output voltage of 1.1 V.The circuit works in two modes:large load current and small load current.The basic principle of LDO is analyzed,the design of the key circuit is detailed,and the feasibility of the design is verified by cadence spectre simulation.In low power consumption mode,the quiescent current can be as low as 3uA.In the full load range,the gain can reach more than 60dB,and the power supply rejection ratio can reach-52dB under light load and-62dB under heavy load.