一种基于ALU运算单元的译码分配电路设计

Design of decoder distribution circuit based on ALU arithmetic unit

本文介绍了一种基于ALU运算单元的译码器分配电路硬件设计,利用verilog硬件描述语言实现整体设计,并利用仿真编译工具对硬件功能进行验证。该译码分配电路实现了对ALU指令行进行逻辑解析,译成各个控制字,控制ALU指令的执行。

This paper introduces a hardware design of decoder distribution circuit based on ALU arithmetic unit.The overall design is realized by verilog hardware description language,and the hardware function is verified by simulation compilation tool.The decoding distribution circuit realizes the logical analysis of ALU instruction line,translates it into each control word,and controls the execution of ALU instruction.