集成计数器异步级联电路仿真问题研究

Research on Simulation Problems of Asynchronous Cascade Circuit of Integrated Counter

在设计任意进制计数器时,若需设计的进制数N大于集成计数芯片最大计数进制M,则需要采用多个芯片通过同步级联或异步级联方法来实现。以异步级联方法设计的任意进制计数器,在进行软件仿真时,由于软件漏洞,计数器并不是从00开始计数,而是从10开始。以此为契机,通过引导学生结合所学知识在设计电路中加入消1功能来解决该问题,达到锻炼学生实践能力的目的。该文针对集成计数器芯片74160探讨在仿真软件中几种消1的方法。

When designing an arbitrary radix counter, if the number of Radix N to be designed is greater than the maximum number M of the integrated counting chip, it is necessary to use multiple chips to achieve it through synchronous cascading or asynchronous cascading. The arbitrary radix counter designed by the asynchronous cascading method, in the software simulation, due to software bugs, does not start counting from 00, but from 10. This paper guides students to add the 1 elimination function to the design circuit to solve this problem, so as to achieve the purpose of training students’ practical ability. Taking the integrated counter chip 74160 as an example, this paper discusses several methods of eliminating 1 in the simulation software.