一种合并状态度量计算的高效并行Turbo码译码器结构设计及FPGA实现

Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations

为满足无线通信中高吞吐、低功耗的要求,并行译码器的结构设计得到了广泛的关注。基于并行Turbo码译码算法,研究了前后向度量计算中的对称性,提出了一种基于前后向合并计算的高效并行Turbo码译码器结构设计方案,并进行现场可编程门阵列(field-programmable gate array,FPGA)实现。结果表明,与已有的并行Turbo码译码器结构相比,本文提出的设计结构使状态度量计算模块的逻辑资源降低50%左右,动态功耗在125 MHz频率下降低5.26%,同时译码性能与并行算法的译码性能接近。

In order to achieve the requirement of high throughput and low-power in wireless communication,a paral-lel Turbo decoder has attracted extensive attention.By analyzing the calculating of the state metrics,a low-resource parallel Turbo decoder architecture scheme based on merging the forward and backward state metrics calculation modules was proposed,and effectiveness of the new architecture was demonstrated through field-programmable gate array(FPGA)hardware realization.The results show that,compared with the existing parallel Turbo decoder archi-tectures,the proposed design architecture reduces the logic resource of state metrics calculation module about 50%,while the dynamic power dissipation of the decoder architecture is decreased by 5.26% at the frequency of 125 MHz.Meanwhile the decoding algorithm is close to the decoding performance of the parallel algorithm.