基于分段电容阵列的改进型逐次逼近型ADC

A Modified SAR ADC with a Piecewise Capacitor Array

为缩短高速模数转换器(ADC)中高位(MSB)电容建立时间以及减小功耗,提出了一种基于分段式电容阵列的改进型逐次逼近型(SAR)ADC结构,通过翻转小电容阵列代替翻转大电容阵列以产生高位数字码,并利用180 nm CMOS工艺实现和验证了此ADC结构。该结构一方面可以缩短产生高位数码字过程中的转换时间,提高量化速度;另一方面其可以延长大电容的稳定时间,减小参考电压的负载。通过缩小比较器输入对管的面积以减小寄生电容带来的误差,提升高位数字码的准确度。同时,利用一次性校准技术减小比较器的失配电压。最终,采用180 nm CMOS工艺实现该10 bit SAR ADC,以验证该改进型结构。结果表明,在1.8 V电源电压、780μW功耗、有电路噪声和电容失配情况下,该改进型SAR ADC得到了58.0 dB的信噪失真比(SNDR)。

To shorten the setting time of the most significant bits(MSBs)capacitors and reduce power consumption in high-speed analog-to-digital converter(ADC),a modified successive approximation register(SAR)ADC stucture with a piecewise capacitor array was proposed.The MSBs digital codes were generated by switching small capacitor array instead of large capacitor array,and the proposed ADC structure was implemented and verified with 180 nm COMS technology.On one hand,the structure can shorten the conversion time in the process of generating MSBs digital codes and increase the quantization speed;on the other hand,it can extend the stabilization time of large capacitors and reduce the load of the reference voltage.By reducing the area of comparator input pairs,the error caused by the parasitic capacitance was reduced,and the resolution of the MSBs digital codes was improved.Meanwhile,the one-time calibration technique was used to reduce the mismatch voltage of the comparator.Finally,the 10 bit SAR ADC was implemented with the 180 nm CMOS technology to verify the modified structure.The results show that the modified SAR ADC achieves a 58.0 dB signal-to-noise distortion ratio(SNDR)under 1.8 V power supply voltage,780μW power consumption and with circuit noise and capacitor mismatch.