基于CPLD的自动变模全数字锁相环设计及仿真

Design and Simulation of Full Digital Phase Locked Loop Based on CPLD

针对传统方法设计的全数字锁相环存在锁相精度不高、锁相速度慢等问题,提出一种基于CPLD实现的新型自动变模全数字锁相环。它可以根据相位误差的大小自动控制数字滤波器的模值,减少在捕捉过程中因相位调整频繁而产生的相位抖动,而设计的基于状态机的数控振荡器可以通过先"粗调"再"精调"来提高锁相精度以及锁定速度。新型锁相环利用QuartusII对Verilog代码编辑综合,并用Modelsim进行了仿真。仿真结果表明,上述锁相环具有抗干扰能力强、动态响应快、锁相精度高的特点,适用于多种应用领域如数字通信、测量和工业控制中。

Aiming at the problems of low phase-locking accuracy and slow phase-locking speed of the all-digital phase-locked loop designed by the traditional method, a new automatic mode-modified all-digital phase-locked loop based on CPLD is proposed. It can automatically control the modulus of the digital filter according to the magnitude of the phase error, and reduce the phase jitter caused by frequent phase adjustment in the capture process. The NC oscillator based on state machine can improve the phase-locked accuracy and locking speed by “coarse adjustment” and “fine adjustment”. The new PLL used QuartusII to edit and synthesize Verilog code, and simulated it with Modelsim. The simulation results show that the phase-locked loop has the characteristics of strong anti-interference ability, fast dynamic response and high phase-locked accuracy, and is suitable for various application fields such as digital communication, measurement and industrial control.