基于TestCenter的仪表转接机制设计与实现

Design and Implementation of Instrument Transfer Mechanism Based on TestCenter

随着包处理芯片设计的需求不断扩大,芯片验证环节的复杂性和难度的提高。一个完整芯片的验证过程会涉及到虚拟功能模型,寄存器传输级RTL,FPGA原型验证不同类型。在进行虚拟功能模型和RTL的验证时会以虚拟仪表的方式进行数据包收发的驱动,FPGA原型验证则以真实仪表的方式进行数据包收发驱动。一旦测试场景发生改变,需要重新编写测试用例,降低测试效率。本文针对验证的重用性差,效率低下等缺点设计了一种虚拟测试仪表,利用TCL语言实现测试脚本和转接脚本,结合网络测试仪表TestCenter实现设计虚拟仪表和真实仪表的转换机制,使得测试用例的可重用性提高,易回归,缩短不同验证阶段的时间。

The increasing demand of packet processing chip design will lead to the increasing complexity and difficulty of chip verification. The verification process of a chip will involve the virtual function model, RTL(Register Transport Level), and FPGA(Field-Programmable Gate Array) prototype verification. During the verification of virtual function model and RTL, packet transceiver drive will be carried out in the way of virtual instrument, while FPGA prototype verification will be carried out in the way of real instrument. Once the test scenario changes, the test cases need to be rewritten to reduce the test efficiency. A virtual test instrument is designed aiming at the disadvantages such as poor reusability and low efficiency of verification. The test script and transfer script are implemented by TCL language, and the conversion mechanism between virtual instrument and real instrument is designed by combining TestCenter, so that the reusability of test cases is improved, regression is easy, and the time of different verification stages is shortened.