基于Knowm忆阻器的2线-9线译码器在FPGA中的设计与实现

Design and implementation of 2-9 line decoder based on Knowm memristor in FPGA

在教学中引入“基于忆阻器的三值数字逻辑电路设计”实验项目,成功地将数字电路、EDA技术与新兴的忆阻器技术相融合。建立和设计了Knowm忆阻器的SPICE模型和FPGA模型,在此基础上,利用前期设计成功的基于忆阻三值数字逻辑电路实现的1线-3线译码器电路,进一步设计了基于三值数字逻辑电路的2线-9线译码器,并对其有效性进行了验证。最后,在FPGA中设计了通过二输入信号点亮9个LED灯的实验,有效验证了2线-9线译码器,提高了传统3线-8线译码器的运行效率,节省集成电路面积,提高电路集成度。

The experimental project of “Ternary Digital Logic Circuit Design Based on Memristor” is introduced into teaching, successfully merges digital circuits, EDA technologies and emerging memristor technologies. The SPICE and FPGA model of the Knowm memristor are established and designed in this paper. On this basis, the successfully designed 1-3 line decoder circuit based on the memristive ternary digital logic circuit is used to design a ternary digital logic circuit based 2-9 line decoder, and its effectiveness has been verified. Finally, an experiment is designed to light up 9 LED lights through two input signals in FPGA. It is effectively confirmed that the 2-9 line decoder effectively improves the operating efficiency of the traditional 3-8 line decoder, saves integrated circuit area and improves circuit integration.