一种适用于CMOS图像传感器的ADC模块设计

Design of ADC module for CMOS image sensor

针对移动终端图像处理传感器对速度和精度的高要求,设计了一种CMOS图像传感器(CIS)的10 bit的ADC模块,在该模块的DAC单元,采用基于多级电流镜的电流型DAC电路的设计,以提高响应速度,同时采用多重采样的方式抑制电路本身的噪声比;在比较器单元,采用了并列开环多级比较器的设计,以达到芯片对速度的要求;在计数器单元,用格雷码进行计数编码,同时对编码结果以阵列的方式进行高速锁存。电路使用SMIC 65 nm的工艺进行设计验证,测试结果表明在500 MHz的工作频率下,ADC的DNL为0.787~1.192LSB,INL为–0.0548%~0.0608%,有效位数为10 bit。

In view of the high requirements for speed and accuracy of image processing sensors in mobile terminals,a 10-bit ADC module of CMOS image sensor(CIS) is designed. In the DAC unit of this module, the current-mode DAC circuit based on multi-stage current mirror is designed to improve the response speed, and the noise ratio of the circuit itself is suppressed by multiple sampling. In the comparator unit, the parallel open-loop multi-stage comparator is designed to meet the speed requirements of the chip. In the counter unit. Gray code is used for counting and encoding, and the encoding results are locked in array at high speed. The circuit is designed and verified using SMIC 65 nm process. The test results show that at the operating frequency of 500 MHz, the DNL of ADC is 0.787~1.192 LSB, the INL is-0.0548%~0.0608%, and the effective number of bits is 10 bit.