摘要
设计了一种基于0.35μm BCD工艺的高效率Buck变换器电路。电路输入电压为10 V~24 V,输出电压为5 V~12 V,最大负载电流为100 mA。采用迟滞控制模式来简化电路结构,降低静态功耗,并通过引入睡眠模式来降低Buck变换器的整体功耗,在Active模式下,静态电流约为110μA,在Sleep模式下,静态电流约为11μA。针对轻负载情况下开关损耗占比较大的现象,针对同步功率管MN设计了浮动栅压电路来减小开关损耗。仿真结果表明,在10 V输入、5 V输出条件下,0.1 mA负载以下的效率可达67.7%,10 mA负载以上的效率均高于91%。
A high-efficiency buck converter circuit was designed in a 0.35 μm BCD process, with 10 V~24 V input voltage, 5 V~12 V output voltage, and 100 mA load current. A simple circuit structure based on the hysteresis control was presented. And the fewer power consumption of the buck converter was achieved by using the sleep mode. In the active mode, the quiescent current was about 110 μA, and in the sleep mode, the quiescent current was about 11 μA. For the phenomenon that the switching loss accounted for a larger proportion under light load conditions, a floating gate voltage circuit for the synchronous power MOSFET MN was designed to reduce the switching loss. Simulation results showed that with 10 V input and 5 V output, the efficiency could reach 67.7% under 0.1 mA load, and the efficiency was higher than 91% above 10 mA load.
作者
刘俊宏
罗萍
赵忠
杨秉中
曹麒
LIU Junhong;LUO Ping;ZHAO Zhong;YANG Bingzhong;CAO Qi(State Key Lab.of Elec.Thin Films and Integr.Dev.,Univ.of Elec.Sci.and Technol.of China,Chengdu 610054,P.R.China;Institute of Electronic and Information Engineering of UESTC in Guangdong,Dongguan,Guangdong 523808,P.R.China)
出处
《微电子学》
CAS
北大核心
2022年第1期1-5,共5页
Microelectronics
基金
广东省基础与应用基础研究基金资助项目(2021A1515011309)。
关键词
迟滞控制
睡眠模式
同步整流
浮动栅压
hysteresis control
sleep mode
synchronous rectification
floating gate voltage
