56 Gbit/s PAM4 CMOS光接收机前端电路设计

Design of a 56 Gbit/s PAM4 CMOS Optical Receiver Front-End

基于65 nm CMOS工艺设计了一种56 Gbit/s PAM4光接收机前端放大电路。前级为差分形式的跨阻放大器,采用共栅前馈型结构降低输入阻抗,并在输入端串联电感,有效提高了跨阻放大器的带宽和灵敏度。后级放大器采用具有线性增益控制的多级级联可变增益放大器,实现对输出摆幅的自动控制。输出缓冲器采用源极退化技术来拓展带宽。后仿真结果表明,在100 fF光电二极管的寄生电容条件下,所设计的光接收机前端电路的-3 dB带宽为24.4 GHz,最大增益达到66 dBΩ,等效输入噪声电流为17.0 pA·Hz;。在输入电流变化及不同工艺角下,输出眼图抖动较小且张开度良好。当电源电压为1.2 V时,不同工艺角下的平均功耗为42.5 mW。

A 56 Gbit/s PAM4 optical receiver front-end was designed in a 65 nm CMOS process. A transimpedance amplifier(TIA) used a common-gate feedforward structure to reduce the input impedance, and an inductor was added at the input port to improve the bandwidth and sensitivity at the input of TIA. A multi-stage variable gain amplifier(VGA) with linear gain control was adopted to adjust the output swing automatically at the post stage. The output buffer(OB) employed the source degeneration technique so as to expand the bandwidth. The post-simulation results showed that the-3 dB bandwidth was 24.4 GHz, the maximum gain reached 66 dBΩ, and the input-referred noise current was 17.0 pA·Hz;with 100 fF photodiode capacitance. Under different process corners and input currents, the output eye-diagrams had small jitter and fine opening degree. The average power consumption was 42.5 mW at different process corners from a voltage supply of 1.2 V.