一种高维持电压的LVTSCR

A LVTSCR with High Holding Voltage

对于工作电压为5 V的集成电路,低压触发可控硅(LVTSCR)的触发电压已能满足ESD保护要求,但其较低的维持电压会导致严重的闩锁效应。为解决闩锁问题,对传统LVTSCR进行了改进,通过在N阱下方增加一个N型重掺杂埋层,使器件触发后的电流流通路径发生改变,降低了衬底内积累的空穴数量,从而抑制了LVTSCR的电导调制效应,增加了维持电压。Sentaurus TCAD仿真结果表明,在不增加额外面积的条件下,改进的LVTSCR将维持电压从2.44 V提高到5.57 V,能够避免5 V工作电压集成电路闩锁效应的发生。

The electrostatic discharge(ESD) protection requirements of integrated circuits with operating voltage of 5 V can be met by the trigger voltage of the low-voltage triggering silicon controlled rectifier(LVTSCR), but the LVTSCR’s low holding voltage always lead to severe latch-up. In order to solve the problems of latch-up, the improved LVTSCR was proposed. An N-type heavily doped buried layer was inserted below the N type well, which changed the current flow path after LVTSCR triggered and reduced the accumulation of holes in the substrate. Thereby the Webster effect of the LVTSCR was inhibited and the holding voltage was increased. Sentaurus TCAD simulation results showed that the holding voltage of the proposed device was increased from 2.44 V to 5.57 V without increasing the additional area, which could avoid the latch-up effect of the integrated circuit with the working voltage of 5 V.