高速高精度比较器设计

Design of High Speed and High Precision Comparator

随着通讯、视频、声纳等技术发展的越来越快,超高速模数转换器(ADC)的设计也日益重要。全并行结构(Full Flash)ADC作为首选结构,被应用于超高速中精度ADC。比较器作为Flash ADC中的重要组成部分,其速度、功耗和噪声决定了ADC的速度、精度和功耗。文中基于预放大再生锁存理论,基于65nm工艺,设计了一种工作在1GHz时钟周期下的超高速CMOS比较器电路,采用电荷存储失调校准技术使得失调电压15小于5.7mV,并采用可再生latch加速比较器输出电压翻转,可以在一个1GHz时钟周期内完成比较,分辨率在0.3mV左右。

With the rapid development of communication,video,sonar and other technologies,the design of ultra-high speed analog-to-digital converter(ADC)is becoming more and more important.As the preferred structure,full Flash ADC is applied to ultra-high speed and medium precision ADC.As an important part of Flash ADC,the speed,power consumption and noise of comparator determine the speed,accuracy and power consumption of ADC.Based on the theory of pre amplification regenerative latch and 65nm process,an ultra-high speed CMOS comparator circuit operating at 1GHz clock cycle is designed.The offset voltage is 15 less than 5.7mV,and the renewable latch is used to accelerate the output voltage reversal of the comparato r.The comparison can be completed in one 1GHz clock cycle,and the resolution is about 0.3mV.