一种宽范围、高精度的带宽自适应式四相DLL

Wide-range and high-accuracy four-phase DLL with the adaptive-bandwidth scheme

NAND Flash存储器具有读写速度高、容量大、可靠性高等优点,被广泛用于固态硬盘、存储卡、U盘等应用中,成为数据中心和消费电子的核心存储元件。开放NAND闪存接口国际标准作为NAND Flash与控制器之间通用接口协议,严格定义了数据传输相关的控制指令、工作时序、电平要求等规范。根据当前ONFI 4.2国际协议标准对NAND Flash高速接口的多相位读写时钟的性能要求,设计了一种具有带宽自适应式延迟链结构的四相输出延迟锁相环,具有宽频锁定和高精度锁定的优点。在设计延迟锁相环中,为了解决宽频率范围下传统延迟链延迟时间有限的问题,提出一种可配置延迟链电路结构,可在不同频段下选择使用相应的延迟单元,从而扩展频率范围并保持精度;提出一款基于鉴频器的自适应控制电路,能跟踪输入时钟频率,自动配置延迟链,实现输出延迟锁相环带宽的自适应。基于SMIC 28nm HKCMOS工艺完成了输出延迟锁相环电路设计。仿真验证结果表明,在25℃、0.9 V电源电压、tt工艺角下,该输出延迟锁相环可产生四相时钟生成,且锁定范围为[22 MHz,1.6 GHz],最高锁定精度为17ps,完全满足ONFI国际标准对多相时钟产生的频率范围和精度要求。

This paper presents a four-phase output delay locked loop(DLL)with one adaptive bandwidth delay chain structure,which is suitable for the clock generation of the NAND Flash high-speed interface circuit meeting the ONFI 4.2 international protocol standard.In order to solve the problem of the limited delay time of the traditional delay chain in a wide frequency range,a configurable delay chain circuit structure is proposed,which can select the appropriated delay units in different frequency bands so that the operating frequency range of DLL is extended and the lock accuracy is maintained.In addition,an adaptive control circuit based on the frequency detector is proposed,which can track the input clock frequency,automatically configure the delay chain,and realize the adaptive bandwidth of the DLL.In the SMIC 28nm CMOS process,the DLL circuit is designed.Simulation results show that the locking range of the DLL is[22 MHz,1.6 GHz]with the maximum locking accuracy being 17 ps at the 25℃/0.9 V power supply and typical process corner.