面向轻量级分组密码的高性能可重构架构

High-Performance Reconfigurable Architecture for Lightweight Block Ciphers

针对目前采用专用集成电路的硬件实现架构难以满足不同应用对灵活性需求的问题,提出一种面向轻量级分组密码的高性能可重构架构(HRALBC).通过分析42种主流的轻量级分组密码算法,提取出算法的模式特征和组合特征;以模式特征结果和组合特征结果为依据设计出可重构处理单元;根据算法映射规律设计可重构处理单元阵列,进而进行架构整体设计.将不同类型算法映射到HRALBC上,验证其功能正确性并分析映射结果.实验结果表明,在TSMC 55 nm CMOS工艺下,HRALBC的工作频率最高可达429MHz,总面积为1.23百万等效门(GE),对于不同密码算法面积效率最高可达22.33Gbit·s^(-1)·MGE^(-1);与Anole相比,对于PRESENT64/80,SPECK64/128和SIMON64/128算法,可重构单元利用率分别提高16.67%,16.67%和13.89%,面积效率分别提高66.64%,66.64%和11.04%.

Aiming at the problem that the current hardware implementation architecture using ASIC is difficult to meet the flexibility requirements of different applications,a high-performance reconfigurable architecture for lightweight block cipher(HRALBC)is proposed.By analyzing 42 mainstream lightweight block cipher algorithms,the pattern features and combination features of the algorithm are extracted;The reconfigurable processing unit is designed based on the pattern feature results and combined feature results;The reconfigurable processing unit array is designed according to the algorithm mapping law,and then the overall architecture is designed.Map different types of algorithms to HRALBC,verify their functional correctness,and analyze the mapping results.The experimental results show that under TSMC 55 nm CMOS process,the working frequency of HRALBC can reach 429 MHz,and the total area is 1.23M equivalent gate(GE).For different cryptographic algorithms,the area efficiency can be up to 22.33Gbit·s^(-1)·MGE^(-1);pared with the Anole,for PRESENT64/80,SPECK64/128 and SIMON64/128 algorithms,the utilization of reconfigurable units is increased by 16.67%,16.67%and 13.89%respectively,and the area efficiency is increased by 66.64%,66.64%and 11.04%respectively.