WiFi-TSN低时延转换架构

WiFi-TSN low latency conversion architecture

无线网络与TSN(Time Sensitive Networking)的融合是目前工业界的关注点之一。传统的基于应用层软件的网关存在CPU利用率高、处理延迟长、性能差等缺点。因此提出了一种WiFi-TSN低时延转换架构,来实现WiFi网络与TSN网络的集成。该架构采用Verilog语言实现,通过硬件来保证通信信道之间可预测的延迟,能够在极短的时间内完成协议转换和协议数据的转发。采用Vivado EDA工具来完成电路的设计,并进行足量的仿真测试来评估电路的端到端延迟性能。

The integration of wireless network and TSN(Time Sensitive Networking)is one of the concerns of industry at present.The traditional gateway based on application layer software has some disadvantages,such as high CPU utilization,long processing delay,poor performance and so on.Therefore,a WiFi TSN low delay conversion architecture is proposed to realize the integration of WiFi network and TSN network.The architecture is implemented in Verilog language,which ensures the predictable delay between communication channels through hardware,and can complete protocol conversion and protocol data forwarding in a very short time.Vivado EDA tool is used to complete the circuit design,and sufficient simulation tests are carried out to evaluate the end-to-end delay performance of the circuit.