0.8~3.2 GHz 6 bit MMIC数字移相器的设计与实现

Design and Implementation of 0.8-3.2 GHz 6 bit MMIC Digital Phase Shifter

基于0.25μm GaAs赝配高电子迁移率晶体管(PHEMT)工艺,研制了一款0.8~3.2 GHz高精度6 bit单片微波集成电路(MMIC)数字移相器。该移相器的5.625°、11.25°和22.5°移相单元采用开关选择型全通/T型低通网络拓扑结构,45°、90°和180°移相单元采用开关选择型全通网络(APN)拓扑结构。通过在APN两侧增加串联电容,在两级APN之间增加高通网络(HPN)及简化APN结构实现了芯片的高移相精度和小型化。移相器驱动单元采用直接耦合场效应晶体管逻辑(DCFL)结构。测试结果表明:在0.8~3.2 GHz频率范围内插入损耗小于18 dB,移相态的均方根(RMS)相位误差小于4.5°,移相寄生调幅小于±1 dB,输入电压驻波比(VSWR)小于1.7,输出VSWR小于1.9。芯片尺寸为5.0 mm×2.0 mm×0.1 mm。

A 0.8-3.2 GHz high-precision 6 bit monolithic microwave integrated circuit(MMIC)digital phase shifter was fabricated with 0.25μm GaAs pseudomorphic high electron mobility transistor(PHEMT)technology.The 5.625°,11.25°and 22.5°phase shifting units of the phase shifter adopted the switch-selective all-pass/T-type low-pass network topology structure,while the switch-selective all-pass network(APN)topology was implemented in 45°,90°and 180°phase shifting units.By the optimized strategy of additional series capacitors on both sides of the APN,inserted high-pass network(HPN)between the two-stage APNs,and structural simplification of the APN topology,high phase shift precision and miniaturization were realized in the chip.The phase shifter drive unit adopted direct coupled FET logic(DCFL)structure.The measurement results show that in the frequency range of 0.8-3.2 GHz,the insertion loss is less than 18 dB,the root-mean-square(RMS)phase error of the phase shift state is less than 4.5°,the phase shift parasitic amplitude variation is less than±1 dB,the input voltage standing wave ratio(VSWR)is less than 1.7,and the output VSWR is less than 1.9.The chip size is 5.0 mm×2.0 mm×0.1 mm.