一种具有噪声整形功能的2bit/cycle SAR ADC的设计

A Design of a 2 bit/cycle SAR ADC Design with Noise Shaping

基于180nm CMOS工艺,设计了一种2 bit/cycle结构的8 bit、100 MS/s逐次逼近模数转换器(SAR ADC).采用两个DAC电容阵列SIG_DAC、REF_DAC实现了2 bit/cycle量化,其中SIG_DAC采用上极板采样大大减少了电容数目,分裂电容式结构和优化的异步SAR逻辑提高了ADC的转换速度.应用一种噪声整形技术,有效提高了过采样时ADC的信噪失真比(SNDR).在1.8 V电源电压和100 MS/s采样率条件下,未加入噪声整形时,仿真得到ADC的SNDR为46.22 dB,加入噪声整形后,过采样率为10时,仿真得到的SNDR为57.49 dB,提高了11.27 dB,ADC的有效位数提高了约1.88 bit,达到9.26 bit.

An 8-bit 100 MS/s successive approximation register analog-to-digital converter(SAR ADC) with2 bit/cycle structure was designed for 180 nm CMOS process. Two DAC capacitor arrays, SIG_DAC and REF_DAC, were used to implement 2 bit/cycle quantization. Upper plate sampling technique was adopted to greatly reduce the number of capacitors in SIG_DAC. Split-capacitor structure and optimized asynchronous SAR logic were arranged to improve the conversion speed of ADC. A noise shaping technique was applied to effectively improve the signal-to-noise-distortion ratio(SNDR) of the ADC at oversampling. The results show that without noise shaping, the proposed ADC can get 46.22 dB SNDR at 100 MS/s rate with 1.8 V supply voltage.Through noise shaping, the simulation results show the SNDR is increased by 11.27 dB to 57.49 dB at an oversampling rate 10, which means the ENOB of ADC is increased by 1.88 bit and reaches 9.26 bit.