用于量子电压基准中约瑟夫森结阵列的CMP平整化工艺研究

Exploring the CMP Process for Josephson Junction Arrays Used in Voltage Standard

化学机械平坦化(chemical mechanical planarization,CMP)工艺处理SiO_(2)绝缘层是一种获得高度集成化超导电路的关键技术,尤其适合于多层堆叠约瑟夫森结阵列器件的平整化。设计了应用于热氧化生长的SiO_(2)薄膜和化学气象沉积生长的SiO_(2)薄膜的CMP工艺,得出两种薄膜的抛光速率分别为2 nm/s和3 nm/s,晶圆的全局材料去除高度差均在20 nm以内。并将CMP工艺应用到约瑟夫森结阵列的制作流程,结单元结构AFM高度轮廓扫描显示台阶高度由240 nm减小到约25 nm,其上的SiO_(2)绝缘层2×2μm^(2)区域内的表面粗糙度为0.535 nm,提供了后续器件制备所需的工艺窗口。

Chemical mechanical planarization(CMP)process on SiO_(2) layer is useful for the yield of highly integrated superconducting circuits especially for the ones with stacked Josephson Junction Arrays.Firstly,the CMP process is explored for the planarization on thermal oxide SiO_(2) and Chemical vapor deposition(CVD)deposited SiO_(2) layers.The test results show that the polishing rates for the two films above are 2 nm/s and 3 nm/s,respectively.And the differences in global material removal height within the wafer are both below 20 nm.Then it is applied to the fabrication process of Josephson Junction Arrays.The Atomic force microscope(AFM)height profile scan on the junction unit indicates that the Step height(SH)is reduced from 240 nm to 25 nm and the surface roughness,which is acquired from a 2×2μm ^(2) area on the capping SiO_(2) isolating layer,is about 0.535 nm,and therefore the CMP process on junction arrays patterned wafer provides sufficient process windows for subsequent fabrication processes.