时钟及面积优化的可配置片上网络路由器

Timing and area optimized re-configurable network-on-chip router

片上网络路由器是实现多核/众核互连的核心电路部件。在介绍同步先进先出缓存器和异步先进先出缓存器的实现电路架构和延迟特点以及片上网络及其路由器架构的基础上,提出了片上网络的时钟优化方案,给出了优化时钟方案下的路由器电路结构,并进行了实现。采用该时钟方案,片上网络路由器间的延迟得以减小。为降低先进先出缓存器的面积开销,进一步提出采用锁存器来实现同步或异步先进先出缓存器,解决了单时钟下的锁存器写问题。更进一步,给出了多个先进先出缓存器的共享实现方案。文章中的方案对开发低功耗嵌入式众核处理器具有直接指导意义。

The Network-on-Chip Router is the key component of multi/many-core processors.In this paper,firstly the schematic architectures of the synchronous First-Input-First-Output(FIFO)buffer and asynchronous FIFO buffer are reviewed with their latencies addressed.Then the architectures of the Network-on-Chip(NoC)and its router are introduced.With the previous foundations,an optimized clock tree distribution scheme,as well as the NoC router implementation under this clock tree distribution scheme,are proposed.With this novel clock tree optimization,the latency of the NoC is greatly reduced.In addition,in order to decrease the area of the register based FIFO,the latch based FIFO is proposed.Single tick latch writing is ensured.And sharing multiple FIFOs is proposed.The proposed techniques are especially useful for embedded low-power many-core processors.