一种采用改良基-2^(6)算法的低复杂度高吞吐量FFT处理器设计

Design of a Low-complexity and High-throughput FFT Processorby Using Modified Radix-2^(6) Algorithm

面向无线个人局域网应用设计了一种高吞吐量、低复杂度的2048点快速傅里叶变换处理器。提出了新型改良基-2^(6)算法用于降低硬件实现复杂度,采用多路径负反馈架构来提高数据吞吐量。为了减少硬件成本,采取正则有符号数常数乘法器替代布斯乘法器完成除旋转因子W_(2048)外所有旋转因子的复数乘法运算。另外,采用了一种减少存储旋转因子W_(2048)系数只读存储器空间的方法,将其存储空间减少为原来的一半。基于QUARTUS PRIME平台的仿真结果显示,工作频率为320 MHz时,最高数据吞吐速率达到了2.6 Gsample/s,而且对比以往的研究方案至少可节约逻辑单元使用量23%,记忆体单元使用量12%。

A high-throughput low-complexity 2048-point fast Fourier transform(FFT)processor is designed for wireless personal area network(WPAN)applications.A novel modified radix-2^(6) algorithm is proposed for reducing the hardware complexity,and multi-path delay feedback(MDF)architecture is adopted for high data throughput.For less hardware-cost,it also uses canonical signed digit(CSD)constant multiplier instead of Booth multiplier to achieve thecomplex multiplications of twiddle factors except W_(2048).In addition,a reduction method of read-only memory(ROM)for storing the coefficients of twiddle factor W_(2048) is adopted,which can halve the ROM size.The simulation result based on QUARTUS PRIME shows that the highest throughput rate is up to 2.6 Gsample/s at 320 MHz.Furthermore,the proposed scheme can reduce at least 23%logic elements and 12%memory bits compared with previous schemes.