3D堆叠封装热阻矩阵研究

Research on Thermal Resistance Matrix of 3D Stacked Package

针对多芯片热阻矩阵的研究模型大多基于多芯片组件模型,多芯片为2D封装类型,而对3D芯片堆叠模型的热阻矩阵研究较少。以3D芯片堆叠模型为例,研究分析了封装器件热阻扩散、热耦合的热阻矩阵。通过改变封装器件内部芯片功率大小,利用仿真模拟计算3D封装堆叠结构的芯片结温。将热阻矩阵计算的理论结果与仿真模拟得到的芯片结温进行对比分析,验证了多层芯片堆叠封装体耦合热阻矩阵的准确性。

Most of the research models for the multi-chip thermal resistance matrix are based on the multi-chip component model,that is,the multi-chip is a 2D package type,and the thermal resistance matrix of the 3D chip stack model is less researched.Taking the 3D chip stacking model as an example,the thermal resistance matrix of the thermal resistance diffusion and thermal coupling of the packaged device is studied and analyzed.By changing the power of the chip inside the packaged device,simulation is used to calculate the chip junction temperature of the 3D package stack structure.The theoretical results of the thermal resistance matrix calculation and the chip junction temperature obtained by the simulation are compared and analyzed to verify the accuracy of the coupled thermal resistance matrix of the multilayer chip stack package.