基于分数阶广义积分器的电网同步技术

A novel grid synchronization technique based on fractional-order generalized integrator

前置滤波结构的锁相环(PLL)是研究电网同步技术的强有力工具.但二阶广义积分器型PLL、复数滤波器型PLL等常用PLL的动态性能因前级结构的截止频率偏低而受到制约.为此,本文提出一种基于分数阶广义积分器的三相PLL技术.该PLL的前级滤波结构由分数阶积分器构成,能够生成两个相位差为45°的斜交信号,经过相关线性运算,可从该对斜交信号中提取出电网电压的正负序分量.结合后级的同步旋转坐标系PLL,建立整个PLL系统的数学模型,并利用三阶最佳设计法对系统进行了校正,确定相关控制参数.研究发现,分数阶广义积分器的截止频率明显高于二阶广义积分器,有利于改善PLL系统的动态品质.仿真和实验结果表明,相比多重二阶广义积分器型PLL,所提PLL的动态性能更佳.

Phase-Locked Loop(PLL)with a pre-filtering stage is a powerful tool to study the grid synchronization technology.However,the dynamic performance of this class of commonly used PLL(e.g.,second-order generalized integrator PLL,complex-coefficient filter PLL)is constrained by the low cut-off frequency of the front-stage structure.Thus,a three-phase PLL technique based on fractional-order generalized integrator is proposed.The front-stage filter of the PLL is composed of fractional-order integrators,which can generate two diagonal signals whose phase difference is 45°.Through the correlation linear operation,the positive-and negative-sequence components of the grid voltage can be extracted from the diagonal signals.Combined with the post-stage synchronous rotating frame PLL,a mathematical model of the entire PLL system is built,and the third order optimal design method is used to correct the system and determine the related control parameters.The study shows that,the cut-off frequency of the fractional-order generalized integrator is obviously higher than that of the second-order generalized integrator,which is helpful to improve the dynamic quality of the PLL system.The simulation and experimental results show that the dynamic performance of the proposed PLL is better than that of the multiple second-order generalized integrator PLL.