ZUC-256流密码轻量级硬件设计与实现

Lightweight Hardware Design and Implementations of ZUC-256 Stream Cipher on FPGA

ZUC‑256是由中国开发的一种应对于5G通信和量子计算机的流密码,该算法主要包含ZUC‑256流密码和一种基于该流密码的完整性算法(EIA3)。本文设计了2种不同的ZUC‑256流密码轻量级电路结构,以及1种基于ZUC‑256流密码的EIA3算法结构。基于FPGA对设计的电路结构和算法结构进行实现,并进行了性能对比。对比结果表明:本文设计的2种电路结构最高达到了6.72 Gb/s的吞吐率,相较于现有的ZUC‑256电路设计在速度上提高了45.24%;本文设计的2种电路相较于之前的ZUC‑128占用资源更少,在面积上分别减少38.48%和30.90%;本文设计的EIA3算法结构仅用0.71μs即可对128位的数据进行加密。

ZUC-256 is a stream cipher developed in China for 5G communication and post-quantum,which mainly includes the ZUC-256 stream cipher and the integrity algorithm(EIA3).This paper designs two kinds of hardware structures of ZUC-256 stream cipher and an EIA3 algorithm structure based on ZUC-256.And then the designed structures are implemented based on PFGA,and their performance is compared.Comparison results show that:The two new ZUC-256 designs reach a throughput of 6.72 Gb/s,which is 45.24%faster than the current ZUC-256 design,and they uses fewer resources than the previous ZUC-128 design,reducing the area by 38.48%and 30.90%,respectively.And the EIA3 algorithm based on ZUC-256 can complete encryption of 128 bit data within 0.71μs.