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CMOS图像传感器的四通道扩展计数ADC设计 被引量:2

A 4-channel extended counting ADC for CMOS image sensor readout
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摘要 面向科研领域应用的CMOS图像传感器,需要具有低噪声、高动态范围和高灰度分辨率的特点.本文分析了多通道扩展计数ADC结构的性能,提出了一种基于相关多采样技术(Correlated Multiple Sampling,CMS)的15位四通道扩展计数ADC.该ADC的4个并行输入通道采用增量型ADC,第二级采用1个循环型ADC在通道间复用.ADC电路基于0.11μm CMOS工艺进行设计,仿真结果显示,在128次多采样下,ADC的分辨率为15位,信号信噪比可提高9.22 dB,此时积分非线性(INL)和微分非线性(DNL)分别为-3.32 LSB和-2.58 LSB,4通道最高采样率为133 KSPS,在3.3 V电源电压下,平均每通道功耗为650μW. A 15-bit 4-channel extended counting(EC)ADC with correlated multiple sampling(CMS)is designed for low-noise column readout in scientific CMOS image sensors(CISs).The 4-channel EC ADC structure is composed of 4 IncrementalΔΣADCs(IADCs)working in parallel and a cyclic ADC to increase the readout speed.The ADC is designed and implemented in a 0.11μm CMOS process.The readout speed of the 4-channel EC ADC is 133KSPS at 5MHz clock frequency.Simulation results show that the maximum INL and DNL of the ADC with 128 times multiple sampling are-3.32 and-2.58 LSBs,and the CMS brings forth a 9.22 dB improvement in SNR.The power consumption is 650μW per channel at 3.3 V supply voltage.
作者 李明 尹韬 蔡刚 高同强 冯鹏 刘力源 吴南健 LI Ming;YIN Tao;CAI Gang;Gao Tongqiang;FENG Peng;LIU Liyuan;WU Nanjian(Aerospace Information Research Institute,Chinese Academy of Sciences,Beijing 100094,China;School of Electronic,Electrical and Communication Engineering,University of Chinese Academy of Sciences,Beijing 100049,China;State Key Laboratory of Superlattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China;School of Microelectronics,University of Chinese Academy of Sciences,Beijing 100049,China;College of Materials Sciences and Opto-Electronic Technology,GUCAS,Beijing 100049,China)
出处 《微电子学与计算机》 2022年第6期115-123,共9页 Microelectronics & Computer
基金 国家自然科学基金(61974146,61874107) 国家重点研发计划项目(2019YFB2204303)。
关键词 CMOS图像传感器 相关多采样 多通道扩展计数ADC 增量型ADC 循环型ADC CMOS image sensors correlated multiple sampling incrementalΔΣADC cyclic ADC multichannel EC ADC
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  • 1Liechti T, Tajalli A, Akgun O C, et al. A 1.8 V 12-bit 230-MS/s pipeline ADC in 0.18 nm CMOS technology. IEEE Asia Pacific Conference on Circuits and Systems, 2008: 21.
  • 2Ahmed I. Pipelined ADC design and enhancement techniques. Springer, 2010.
  • 3Amirabadi A, Tabrizi M M, Sharifkhani M, et al. A 10 b, 40 Msample/s, 25 mW pipeline analog to digital converter. IEEE Canadian Conference on Electrical and Computer Engineering, 2004,4: 1989.
  • 4Diaz-Madrid J A, Neubauer H, Hauer H, et al. Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. Proceedings of the Conference on Design, Automation and Test in Europe, European Design and Automation Association, 2009: 369.
  • 5Kwok P T F, Luong H C. Power optimization for pipeline analog-to-digital converters. IEEE Trans Circuits Syst II: Analog and Digital Signal Processing, 1999, 46(5): 549.
  • 6Li B, Li Z, Li Y, et al. A 57 mW 10-bit 80-MS/s pipeline ADC adopting improved power optimization approach. IEEE 7th International Conference on ASIC, 2007: 616.
  • 7Min B M, Kim P, Bowman III F W, et al. A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC. IEEE J Solid-State Circuits, 2003,38(12): 2031.
  • 8Device A. Ad9218.
  • 9Xue F, Wei X, Hu Y, et al. Design of a 10-bit 50MSPS pipeline AEC for CMOS image sensor[C] ff Industrial Electronics and Applications (ICIEA), 2014 IEEE 9th Conference on. [s. 1. ]: IEEE, 2014: 891-895.
  • 10Lee B G, Min B M, Manganaro G, et al. A 14b 100MS/s pipelined ADC with a merged active S/H and first MDAC[C] // Solid-State Circuits Confer- ence, Digest of Technical Papers IEEE International. Boston: IEEE, 2012 : 248-611.

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