DHR TDC芯片的性能测试

Testing and Evaluation of the DHR TDC ASIC

TDC(time-to-digital converter)作为基于信号甄别和时间数字转换的时间测量技术路线的主要组成部分之一,至今在诸多领域中都具有广泛的应用。本实验室对高精度时间测量TDC ASIC(Application Specific Integrated Circuit)进行了深入研究,在180 nm CMOS工艺下完成了基于DLL(Delay-Locked Loop)结构的原型芯片的设计,芯片命名为DHR TDC。为了评估原型芯片的相关性能以推进下一步的改版设计,设计了测试电子学模块,构建了相应的电子学测试系统并完成了性能测试。测试结果表明,该TDC具有较好的性能,在实现156 ps的bin size基础上时间精度好于60 ps RMS。同时该TDC在20μs的动态范围下具有较好的线性,其DNL(Differential NonLinearity)和INL(Integral NonLinearity)分别好于0.13和0.15 LSB (Least Significant Bit)。

As one of the key components in high precision time measurement based on discrimination and time digitization,the time-to-digital converter(TDC) is widely used in many fields. This paper presents the design and testing of a DLL based TDC prototype ASIC named DHR TDC with a large detectable range and high resolution in 180 nm CMOS technology. A test module was designed and the test platform was set up for the TDC performance evaluation. Test results indicate that this TDC achieves a time resolution of better than 60 ps RMS with an averaged bin size of around 156 ps, as well as a measurement dynamic range of up to 20 μs, and its differential nonlinearity(DNL) and integral nonlinearity(INL) are better than 0.13 LSB and 0.15 LSB, respectively.