联动薄膜电容式压力敏感芯片研制

Development of Capacitive Pressure-sensitive Chip with Linkage Film

文中对联动薄膜电容式压力敏感结构进行研究,结构中的上极板和下极板均感压可动,随着压力载荷的增加,上下极板绝缘接触后,通过下极板对上极板形变状态的调节作用,有效增加了线性响应范围,提高了线性度。同时,结构中采用带有残余压应力的感压上极板来代替无应力的感压上极板,通过仿真计算表明,相较于无应力的感压上极板,当感压上极板中存在残余压应力时,输出电容具有更好的线性响应。通过采用SOI材料的单晶硅薄膜结合硅-硅直接键合技术试制了量程为0~80 kPa压力敏感芯片,并给出了工艺流程。测试结果表明,在20~64 kPa压力范围下,所试制压力敏感芯片的灵敏度为0.057 pF/kPa,非线性度为3.1%。

In this paper,the capacitive pressure sensitive structure with linkage film was studied.The top and bottom electrode plates in this structure were both pressure-sensitive and movable.As the load pressure increased,after the top electrode plate contacted the bottom electrode plate with the insulation layer,the top electrode plate was deformed by the bottom electrode plate.The adjustment function of the state effectively increased the linear response range and improved the linearity.At the same time,the top electrode plate with residual compressive stress was used in this structure to replace the stress-free top electrode plate.Simulation calculations show that a pressure-sensitive top electrode plate with residual compressive stress can provide superior linear response than a stress-free top electrode plate.A pressure sensitive chip with a full-scale range of 0~80 kPa is trial-produced by using SOI wafers combined with silicon-silicon fusion bonding technology,and the process flow is given.The test results show that,in the pressure range of 20~64 kPa,the sensitivity of the trial-produced pressure-sensitive chip is 0.057 pF/kPa,and its non-linearity is 3.1%.