锁相环环路特性分析

Analysis of Phase Locked Loop Loop Circuit

首先给出了电荷泵锁相环(Phase Locked Loop,PLL)的基本电路结构,然后基于三阶有源环路滤波器推导了整个电路的传输函数,并对该传输函数的零极点位置进行了分析,最后利用该方法设计一款锁相环产品,鉴相器频率为50 MHz,锁定频率为8550 MHz,相位噪声为-99dBc/Hz@1kHz和-104dBc/Hz@10kHz,满足工程应用需求。

Firstly,the basic circuit structure of Phase Locked Loop(PLL)is presented,and then based on the third order active loop filter,the transmission function of the whole circuit is guided,and the zero and pole positions of the transmission function are analyzed.Finally,a phase locked loop is designed with this method.The frequency of phase detector is 50 MHz,the locking frequency is 8550 MHz,and the phase noise is-99DBC/Hz@1kHz and-104DBC/Hz@10kHz,Meet engineering application requirements.