一种高效监测工艺制程的电路设计

An Efficient Testing Circuit for Process Characterization

随着摩尔定律的发展,集成电路中的晶体管及其互联金属尺寸逐渐减小。为实现这些纳米级尺寸结构,就需要更复杂的工艺制程,但随之而来的是芯片中缺陷的增加和良率的下降。为解决这一问题,作者设计一种高效的用于监测后道工艺制程的电路,可以同时监测大量样品,并准确发现有缺陷的结构。相较于传统的两端法测试方法,作者提出的电路和相应测试方法在相同面积情况下可以多放36%的测试样品,测试同等数量样品可以节省近70%的总测试时间,并通过投片验证。本文的设计有助于快速发现工艺中的缺陷并进行优化迭代,最终提升晶圆厂良率,提高产品竞争力。

As the predication of Moore's law,the size of transistor and connecting metal inside the integrated circuit is becoming smaller gradually.In order to achieve these nanometers size structure,many complex and sophisticated pro-cess has been developed.However,the defects in the chip are increasing dramatically,while the yield decreasing with more complexity of the process.In this paper,the author designed an efficient testing circuit for back end of Line pro-cess characterization.The circuit can not only monitor a large number of samples at the same time,but also accurately find the defective structure.Compared with the traditional methods,the proposed circuit and testing methods can measure 36%more samples with the same area,and total testing time can save nearly 70%with the same number of samples.These are verified by silicon tape-out.This design is helpful to find the defects in the process and quick it-eration,which will finally improve the yield and competition of foundry.