一种优化FinFET工艺中冗余电容的方法

A Method for Optimization of Redundant Parasitic Capacitance in FinFET Process

在目前集成电路先进制造工艺下,普遍采用鳍式场效应管(FinFET)结构作为最基本的逻辑器件,以获得更高的制造密度和更强的沟道控制能力。FinFET制造工艺中通常包含双扩散区隔离(Double Diffusion Break,简称DDB)和单扩散区隔离(Single Diffusion Break,简称SDB)两种扩散隔离工艺结构。SDB结构相较于DDB结构具有更高的逻辑器件集成密度,但不足之处在于实际应用中会引入额外的冗余电容,而SDB结构中的冗余电容会导致功耗和延时的增加,降低器件性能。本文提出一种使用栅极切割工艺结合M0G部分接触工艺的方案,消除电路中SDB结构引入的冗余电容,从而有效地提高数字电路翻转速度,降低动态功耗。通过对一个2输入数据选择器(MUX2)进行优化并仿真后发现,若仅仅将SDB结构改成DDB结构,S-Z路径上的电容和动态功耗可以降低12.7%,但会额外牺牲单元面积9.1%;若采用M0G与栅极部分接触方案优化设计和工艺,S-Z路径可以节省18.7%的动态功耗,并提升16.2%的速度,同时单元面积保持不变。利用该设计方案优化部分单元电路,产生新的单元库,并应用于A72 CPU核的纯逻辑模块。实验表明A72 CPU核的功耗降低了2.6%,性能提升了1.77%。

Fin field-effect transistor(FinFET)is widely used as the basic bulding block in current advanced process technology to achieve higher logic density and stronger channel controllability.Generally,two diffusion isolation pro-cess structures are applied in FinFET manufacturing process,including double diffusion break(DDB)and single diffusion break(SDB)structures.Compared with DDB process,the SDB process could further improve the integration density of logic devices,but redundant parasitic capacitance is also introduced in fabrication process,which results in the increase in power consumption and the decrease in device perfomance.In this paper,a novel connection method is proposed with the implementation of gate-cut process and M0G partial landing to enhance the switching speed of digital circuits.Moreover,the dynamic current and power consumption could be reduced by eliminating the redundant capacitance from the circuit nets as well.A 2-way multiplexer(MUX2)is then optimized and simulated.The capaci-tance and dynamic power consumption of S-Z path can be reduced by 12.7%,while the cell area is increased by 9.1%by only replacing DDB process with SDB process.When M0G partial landing on gate is implemented,the power con-sumption can be reduced by 18.7%and the speed is accelerated by 16.2%with the same design area.By utilization of our methodology,the standard cells are optimized and a new library is generated for the use in the pure logic module of A72 CPU core.Experimental results show that the power consumption of A72 CPU core is reduced by 2.6%and the overall performance is enhanced by 1.77%.