一种流水线型ADC的时序改进技术研究

Study on a Timing Optimization Technique for Pipelined ADC

对一种流水线型模数转换器(ADC)的时序电路进行了改进研究。改进时序延长了余量增益单元MDAC部分加减保持相位的时长,可以在不增加功耗与面积的情况下,将一种10位流水线型ADC在20 MS/s采样率下的有效位(ENOB)从9.3位提高到9.8位,量化精度提高了5%;将该ADC有效位不低于9.3位的最高采样率从21 MS/s提高到29 MS/s,转换速度提高了35%。ADC的采样频率越高,改进时序带来的效果越显著。该项技术特别适用于高速高精度流水线型ADC,也为其他结构ADC的高速高精度设计提供思路。

A timing optimization technique was studied based on 10 bit pipelined ADC. The technique prolonged the phase holding time of MDAC. Without increasing power consumption and chip area, the effective numbers of bit(ENOB) was increased from 9.3 bit to 9.8 bit under 20 MS/s sampling rate of a 10 bit pipelined ADC, and the accuracy was improved by 5%. The maximum sampling rate of the ADC was increased from 21 MS/s to 29 MS/s with ENOB no less than 9.3 bit, and the speed was increased by 35%. The higher the sampling rate of ADC, the more significant the improvement effect was. This technique was especially suitable for high-speed and high-precision pipelined ADC, and also provided ideas for high-speed and high-precision design optimization of ADC.