基于MASH结构的24 bit Σ-Δ A/D转换器

A MASH Architecture 24 bit Σ-Δ A/D Converter

设计了一种离散时间型24位Σ-ΔA/D转换器。该A/D转换器基于级联噪声整形(MASH)结构设计,整个转换器由前置可编程增益放大器、级联调制器和数字抽取滤波器等模块组成。该A/D转换器采用标准0.18μm CMOS工艺实现,版图总面积为6 mm^(2)。测试结果表明,在16 kS/s输出数据速率下,该A/D转换器的信噪比为106 dB,无杂散动态范围为110 dB,功耗仅为20 mW。

A discrete-time Σ-Δ A/D converter was presented. The A/D converter was based on the cascade noise shaping(MASH) structure design. The whole converter was composed of programmable gain amplifier, cascade modulator and digital decimation filter. The A/D converter was implemented in a standard 0.18 μm CMOS technology, and the chip area was 6 mm^(2). Test results showed that the A/D converter had an SNR of 106 dB, an SFDR of 110 dB, a power consumption of only 20 mW at 16 kS/s output data rate.