一种基于VCM开关切换的12位20 MS/s SAR ADC

A VCM-Based 12 bit 20 MS/s SAR ADC

设计了一种12位、采样率为20 MS/s的逐次逼近型模数转换器(SAR ADC)。整体电路为全差分结构,采用了一种基于VCM开关切换的分段式电容阵列。同时,比较器结合了前置运放和动态锁存器,与异步时序相配合,实现了SAR ADC高速工作。此外,采样电路采用栅压自举技术,提高采样的线性度。芯片基于TSMC 180 nm 1P5M CMOS工艺设计。仿真结果表明,当采样率为20 MS/s时,SAR ADC有效位数为11.94 bit,无杂散动态范围为86.53 dBc,信噪比为73.66 dB。

A 12-bit successive approximation register analog to digital converter(SAR ADC) with a sampling rate of 20 MS/s was designed. The whole circuit was a fully differential structure, and a segmented capacitor array utilizing VCM-based switching scheme was used. At the same time, the comparator combined the pre-amplifier with the dynamic latch, so the SAR ADC achieved high speed operation with asynchronous timing. In addition, the sampling circuit adopted the bootstrapped switch to improve the linearity of sampling. The chip was designed in a TSMC 180 nm 1 P5 M CMOS process. The simulation results showed that when the sampling rate was 20 MS/s, the effective number of bit of the SAR ADC was 11.94, the spurious free dynamic range was 86.53 dBc, and the SNR was 73.66 dB.