期刊文献+

面向E级计算的功耗管理技术 被引量:3

Power Management Technology for Exascale Computing
下载PDF
导出
摘要 E级计算机的构建面临严峻的“功耗墙”问题.为了应对功耗挑战,本文面向神威E级系统提出了一套低功耗管理体系.该体系采用软硬件协同的多层次低功耗管理机制,主要技术包括高能效基础设施设计、低功耗编译优化和细粒度功耗运行时管理,在系统功耗量化监测技术支撑下实现软硬件协同能耗控制集成,具有功能层次多、覆盖面广、节能效果明显的特点.本文基于神威E级原型超级计算机进行了系统验证,实验结果证明本文提出的低功耗管理体系能够显著降低系统功耗,并且可扩展性良好,在大规模系统中具有广泛的适应性,能够支撑E级计算机绿色运行. As it is known to all,Power Wall is one of the biggest challenges that people have to face when they are building an Exascale computer system.Thousands of works have been done to reduce the power or energy consumption on all hierarchies of the computer system.However,the existing studies only focus on the traditional architecture.In the Exascale era,as the scale and complexity of systems increase,the practicability is not guaranteed.In order to overcome the aforementioned challenge,we propose a low power management system for the Sunway Exascale system.The low power management system has a several of innovative technologies,including the high energy-efficient infrastructure design,the low-power compilation optimization and the fine-grained power consumption runtime management technology.First,the high energy-efficient infrastructure design focuses on the power supply and cooling subsystem to achieve the high efficient power conversion by monitoring the power level of the whole system.Second,the low-power compilation optimization is proposed to reorder the instruction sequence elegantly which is based on the innovation design of the underlying architecture.Specifically,the memory addresses of the instructions are reassigned to reduce the data movement in the high speed LDM(Local Device Memory).The instructions are also scheduled to meet the constraints of the register bypassing requirements,and the loop structure is reshaped to let the instructions of the loop stay in the L0 cache as long as possible.We utilize this low-power compilation optimization by reducing some redundant operations in the processors in order to improve the power efficiency.Third,based on the Dark Silicon technology,the fine-grained power consumption runtime management consists of multilevel low power scheduling in the computer system.In the node level,with the help of the operating system,an automatic quick switch of the power supply for each node is introduced according to the status of the node.In the job level,the frequency adjustment and the sleep/run state management for the many-core array is proposed so that the many-core processors can be turned into a low power status when no workload needs to be executed.In the system level,we introduce a hierarchy parallel framework to achieve the power assignment for the high scale job management,in which the resources are grouped into several small sets,and the status of the resource group is adjusted individually.What is more,the proposed low power management system realizes the integration of hardware and software collaborative energy consumption control under the support of the system power consumption quantification monitoring technology.Our system shows some great advantages such as multiple hierarchies,wide coverage and energy saving.We do many experiments on the Sunway Exascale Prototype Supercomputer and the results show that the low-power management system proposed in this paper can significantly reduce the power consumption of the system.The system also has good scalability and can be widely adapted to various scenarios in the large-scale systems.The low power management system provides a practical way to alleviate the power constraint dilemma in the future Exascale computing field.
作者 高剑刚 龚道永 吴伟 郑岩 朱琪 王飞 郑方 金利峰 GAO Jian-Gang;GONG Dao-Yong;WU Wei;ZHENG Yan;ZHU Qi;WANG Fei;ZHENG Fang;JIN Li-Feng(National Research Center of Parallel Computer Engineering and Technology,Beijing 100190)
出处 《计算机学报》 EI CAS CSCD 北大核心 2022年第7期1373-1383,共11页 Chinese Journal of Computers
基金 国家重点研发计划项目(2016YFB0200500)资助。
关键词 E级计算机 异构众核处理器 功耗管理 编译优化 运行时优化 exascale computer heterogeneous many-core processor power management compilation optimizing runtime optimizing
  • 相关文献

参考文献3

二级参考文献33

  • 1易会战,杨学军.高性能微处理器的微体系结构能量有效性[J].计算机学报,2004,27(7):874-880. 被引量:2
  • 2黄海林,范东睿,许彤,唐志敏.嵌入式处理器中访存部件的低功耗设计研究[J].计算机学报,2006,29(5):815-821. 被引量:11
  • 3张戈,胡伟武.高性能通用处理器中的漏电功耗优化[J].计算机学报,2006,29(10):1764-1771. 被引量:2
  • 4Esmaeilzadeh H,Blem E,St Amant R,et al.Dark silicon and the end of multicore scaling//Proceedings of the 38th Annual International Symposium on Computer Architecture (ISCA).San Jose,USA,2011:365-376.
  • 5Bergman K,Borkar S,Campbell D,et al.Exascale compu tingstudy:Technology challenges in achieving exascale systems.Arlington,VA,USA:Defense Advanced Research Projects Agency Information Processing Techniques Office (DARPA IPTO),Technology Report:TR-2008-13,2008.
  • 6Kaxiras S,Martonosi M.Computer architecture techniques for power efficiency:Synthesis lectures on computer archi tecture.San Rafael,California,USA:Morgan & Claypool Publishers,2008.
  • 7Carter N P,Agrawal A,Borkar S,et al.Runnemede:An architecture for ubiquitous high performance computing// Proceedings of the 19th International Symposium on High Performance Computer Architecture (HPCA2013).Shenzhen,China,2013:198-209.
  • 8Keckler S W,Dally W J,Khailany B,et al.GPUs and the future of parallel computing.IEEE Micro,2011,31 (5):7-17.
  • 9Hayenga M,Lipasti M H,Reddy V.Revolver:Processor architecture for power efficient loop execution //Proceedings of the 20th International Symposium on High Performance Computer Architecture (HPCA2014).Orlando,USA,2014:591-602.
  • 10Solomon B,Mendelson A,Ronen R,et al.Micro operation cache:A power aware frontend for variable instruction length ISA.IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2003,11(5):801-811.

共引文献35

同被引文献4

引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部