一种基于FPGA+DDR3的雷达数据高速重排方法

A High-Speed Rearrangement Method of Radar Data Based on FPGA+DDR3

由于现场可编程门阵列(FPGA)处理速度快、数据吞吐量大,双倍速率同步动态随机存储器(DDR)存储容量大、价格低,因此多数雷达均采用FPGA+DDR3的架构实现数据重排。但由于DDR3跳变地址读写效率低,导致重排速度慢,已不能满足现代雷达对信号处理速度提出的要求。因此本文提出了一种高速重排方法,通过数据拼接、按块读取、设计同时读写时序等操作,可大幅度减少地址跳变次数,提升重排速度,以满足现代雷达对信号处理速度提出的要求。

Due to the fast processing speed and large data throughput features of FPGA and the large storage capacity and low price features of DDR3,most radars adopt FPGA+DDR3 architecture to realize data rearrangement.However,the low efficiency of DDR3 bus when jump addresses read or write leads to slow rearrangement speed,which cannot meet the requirements of modern radar for signal processing speed.Therefore,a high-speed rearrangement method was proposed in this paper,which can greatly reduce the number of jump addresses and improve the rearrangement speed by data splicing,block reading and timing optimization,so as to meet the requirements of signal processing speed of modern radar.