基于CPCIe高速总线的机载多核计算处理平台

Multi-core computing and processing platform based on CPCIe high speed bus in airborne applications

由于中小型飞机航空电子系统对计算处理平台体积、功耗和重量方面的严格限制,有必要对计算处理平台进行高性能、小型化、低功耗的针对性设计。研究了一种基于CPCIe(CompactPCI Express)高速总线和多核处理器的机载计算处理平台架构,攻克了多核处理和CPCIe高速信号完整性在航空电子系统中的适应性问题,设计并实现了一款基于CPCIe高速总线的分布式机载多核计算处理平台,对CPCIe总线信号完整性进行了仿真和测试,最后在航空电子系统中对计算处理平台进行实施验证。相比于传统的联合式架构和综合模块化架构,计算处理平台的性能功耗比分别提升约7倍、5倍,性能体积比分别提升约24倍、2倍,性能重量比分别提升约15倍、1.7倍,可以满足中小型飞机航空电子系统对计算处理平台小型化、低功耗和高性能的需求,具有较好的工程应用参考价值,在航空领域具有广泛的应用前景。

As the avionics system of small and medium aircraft has strict restrictions on the volume,power consumption and weight of the computing and processing platform,it is necessary to design the computing and processing platform with high performance,miniaturization and low power consumption.An airborne computing and processing platform architecture based on the CPCIe(CompactPCI Express) high-speed bus and multi-core processor is studied.The adaptability of multi-core processing and high-speed signal integrity to the avionics system is realized.A distributed airborne multi-core computing platform is designed and implemented based on the CPCIe high-speed bus.Signal integrity of the CPCIe bus is simulated and tested.The computing processing platform is implemented and verified in the avionics system.Compared with the traditional joint architecture and integrated modular architecture,the performance per watt of the platform proposed is improved to about 7 times and 5 times,the performance per cubic centimeter is improved to about 24 times and 2 times,and the performance per gram is improved to about 15 times and 1.7 times.The platform can meet the requirements of small and medium aircraft avionics system for miniaturization,low power consumption and high performance of the computing and processing platform,showing good applicability in the aviation field.