OpenVX特征抽取函数在可编程并行架构的实现

Parallel Implementation of OpenVX Feature Extraction Functions in Programmable Processing Architecture

针对数字图像处理计算量大、串行结构计算速度慢等特点,完成了最新的开源OpenVX计算机视觉加速规范1.3中底层特征抽取核函数的并行实现,使用自主设计的OpenVX可编程并行处理器进行了验证。在对图像的底层特征提取中,前期滤波及平滑处理选择OpenVX规范1.3中基本像素点处理函数ColorConvert(颜色转换)和局部图像处理函数GaussianFilter(高斯滤波)、MedianFilter(中值滤波)等,核心的特征抽取操作选择HarrisCorners(哈里斯角点检测)和CannyEdgeDetector(坎尼边缘检测)核函数,通过将计算量大的复杂结点拆分为多个简单结点,构建不同的基于图的执行模型,并映射在OpenVX并行处理器上,分别实现图像的边缘检测和特征点抽取。使用Verilog语言设计整体硬件电路,经Xilinx公司的FPGA芯片xcvu440-flga-2892-2-e综合验证,与串行映射结构相比,所选核函数在OpenVX可编程并行处理器上的并行加速比最高可达14.269。实验结果表明,OpenVX规范1.3中的核函数尤其是复杂核函数能够在本并行处理结构上达到预期的加速效果,且并行与串行结构加速比呈线性增长。

Aiming at the mass computing and slow speed of serial structure calculation of digital image processing,parallel implementation of underlying feature extraction kernel functions in the latest open source OpenVX specifi-cation 1.3 is completed,and the verification is carried out with the self-designed OpenVX programmable parallel processor.In the underlying feature extraction of the image,the basic pixel processing function Color Convert,the local image processing functions Gaussian Filter and Median Filter of OpenVX specification 1.3 are selected for fil-tering and smoothing.Harris Corners and Canny Edge Detector are selected for feature extraction.By dividing the complex nodes with large amount of computation into several simple nodes,different graph execution models are constructed and mapped on the OpenVX parallel processor to realize image edge detection and feature point extraction respectively.Verilog is used to design the hardware circuit,and the FPGA chip xcvu440-flga-2892-2-e of Xilinx has comprehensively verified that,compared with the serial mapping structure,the parallel acceleration ratio of the se-lected kernel function on the OpenVX programmable parallel processor can be up to 14.269.Experimental results show that the kernel functions in OpenVX specification 1.3,especially the complex kernel functions,can achieve ex-pected acceleration effect in this parallel processing structure,and the speedup ratio of parallel and serial structures increases linearly.