基于防错锁控制结构的延迟锁相环设计

Design of Delay Locked Loop Based on Anti-mislock Control Structure

提出了一种防错锁控制结构,有效地解决了延迟锁相环教学和实践过程中出现的死锁定或谐波锁定等问题。基于0.18μm CMOS工艺,完成了电路设计、版图设计以及后仿真。后仿真结果表明,在理想的时钟驱动下,延迟锁相环能准确锁定,确定性抖动为3.82 ps,自身随机性抖动为2 ps,可提供低抖动多相位的时钟。有助于学生理解掌握延迟锁相环精度和速度等设计要点,具有一定的教学指导意义。

In this paper,an error-proof lock control structure is proposed,which effectively solves the problems of dead lock or harmonic lock in the delay-locked loop during teaching and practice.Based on 0.18μm CMOS technology,circuit design,layout design and post-simulation are completed.The post-simulation results show that under the ideal clock drive,the delay-locked loop can lock accurately,the deterministic jitter is 3.82 ps,and its own random jitter is 2 ps,which can provide a low-jitter multi-phase clock.This paper helps students to understand and master the design points of delay-locked loop accuracy and speed,and has certain teaching guiding significance.