基于FPGA的数字时钟设计

Design of Digital Clock Based on FPGA

目的 设计一个具有计数、调时功能的数字时钟,以二十四小时为一个周期循环计数。方法 用Verilog HDL硬件描述语言,在Quartus Ⅱ开发环境下采用自顶向下的方法设计数字时钟;设计主要包括分频模块、计数校时模块和译码显示模块三部分;分频模块把50 MHz的输入信号分频得到1 Hz的时钟信号,计数校时模块可以计数和调整时钟、分钟、秒钟的时间,然后通过译码显示模块在FPGA开发板上显示。结果 由Modelsim软件对各模块进行仿真测试可知,该系统基本实现了数字时钟的功能,满足设计要求。结论 Verilog HDL与具体电路无关,在Quartus Ⅱ开发环境下,大大地提高了设计的效率。

In this paper, Verilog HDL hardware description language is used to design a digital clock in Quartus-Ⅱ environment by top-down method.It has the function of counting, timing and is tied to the 24-hour continue cycle.Its design includes three parts: frequency division module, the counting and timing module and segment code display module.The frequency division module is to divide 50 MHz input signal into 1 Hz clock signal and output it to the counting and timing module.The counting and proofreading module can count and adjust the clock, minutes and seconds.Then, they are displayed on the FPGA development board through the segment code display module.According to the simulation test of each module with the Modulsim software, the function of the digital clock is basically realized and is met the design requirements.Because Verilog HDL has nothing to do with circuits, the Quartus Ⅱ development environment greatly improves the design efficiency.