Dither技术在16位奈奎斯特模数转换器中的应用

Dither Technique Applied In Nyquist ADC

针对传统随机化(Dither)技术会引入额外噪声、占用转换周期以及缩小量化范围的问题,提出应用于高精度逐次逼近型模数转换器(Successive Approximation Analog to Digital Converter, SAR ADC)的dither新技术。该技术在传统二进制权重的电容型数模转换器(Digital to Analog Converter, DAC)中引入增量式电容阵列,形成混合型电容阵列,并随机化大电容的误差,以削减较大的谐波,且不占用额外量化周期。为验证该dither新技术,利用MATLAB进行仿真,并基于55 nm CMOS工艺,设计了一个16位的二级逐次逼近型模数转换器。仿真结果显示,所设计的ADC使用1.2 V和3.3 V电源供电,在采样速率1.25 MHz,输入信号为107 kHz的条件下,消耗了3.1 mA电流,得到了94.0 dB的信纳失真比(Signal to Noise and Distortion Ratio, SINAD)。

Aiming at the problems of bringing additional noise, occupying conversion period and reducing quantization range faced by typical dither technique. An improved dither technique used in a high-resolution SAR ADC is proposed. It modifies a binary weighted capacitor array into the hybrid capacitor array which has binary-weighted capacitors and incremental capacitors, and dithers large capacitors to reduce the largest harmonics without occupying extra conversion period. To verify the proposed dither method, MATLAB simulations are done and a 16-bit SAR ADC based on a 55 nm CMOS process is designed. Simulation results show that the ADC uses supply voltages of 1.2 V and 3.3 V. When the sampling rate is 1.25 MHz and the input signal is 107 kHz, it consumes 3.1 mA current and obtains 94 dB SINAD.