数字信道化高效结构设计及FPGA实现

Design and FPGA Implementation of High-Efficient Structure of Digital Channelization

针对宽带接收机中处理多个同时到达信号时的逻辑资源消耗大、实时性差、配置不灵活等问题,从多相滤波和采样率等价交换原理出发,对接收机前端信道化过程开展研究。提出了包含移位抽取模块、多相滤波模块和全并行快速傅里叶变换(FFT)模块的数字信道化高效实现结构;利用基于现场可编程门阵列(FPGA)的硬件描述语言实现了该高效结构。最后,给出了仿真验证和在线测试的结果,验证了该高效结构实现方式合理。在满足宽带接收机处理多个同步到达信号的同时,有效提高了处理速率,降低了资源消耗,为后续基带信号处理预留了更多的硬件资源。

Aiming at the problems of large consumption of logic resources, poor real-time performance and inflexible configuration when multiple signals arrive at the same time in wideband receiver, the channelization process of receiver front-end is studied based on the principle of polyphase filterter and equivalent exchange of sampling rate.An high-efficient structure of digital channelization is proposed, which includes shift decimation module, polyphase filter module and fully parallel fast Fourier transform(FFT) module.The high-efficiency structure is realized by using the hardware description language based on field programmable gate array(FPGA).Finally, the simulation and on-line test results are given to verify the rationality of the university structure.While satisfying the broadband receiver to process multiple simultaneous arrival signals, it effectively improves the processing rate, reduces the resource consumption, and reserves more hardware resources for subsequent baseband signal processing.