RISCV指令集的SM4专用协处理器设计

Design of SM4 Special Coprocessor Based on RISCV Instruction Set

针对进口信息产品存在安全隐患以及RISCV架构在安全领域产品严重缺乏的问题,设计了一种可以提高SM4密码算法运算效率且完全自主可控的协处理器。协处理器采用三级流水线结构提高指令执行效率,扩展5条自定义指令用于完成SM4运算,内部封装SM4运算单元以减小对数据通路的影响、便于后续扩展。借助FPGA开发板,在50 MHz的时钟频率下进行验证。验证结果表明,与无指令扩展的处理器相比,本设计密钥扩展运算效率提高了5.8倍,加密运算效率提高了5.5倍,解密运算效率提高了6.4倍,所提出的方案可显著提高SM4运算效率。

In view of the hidden danger of imported information products and the serious shortage of RISCV architecture products in the field of security,a fully autonomous and controllable coprocessor is designed to improve the efficiency of SM4 cryptography algorithm.The threelevel pipeline structure is adopted to improve the instruction execution efficiency,and five customized instructions are extended to complete SM4 operation.The SM4 operation unit is encapsulated internally to reduce the impact on the data path and facilitate subsequent expansion.With the help of FPGA development board,verification is carried out at 50 MHz clock frequency.The results show that compared with the processor without instruction extension,the efficiency of key expansion operation is increased by 5.8 times,the efficiency of encryption operation is increased by 5.5 times,and the efficiency of decryption operation is increased by 6.4 times.The proposed scheme can significantly improve the efficiency of SM4 operation.