摘要
嵌入式Flash由于成本、存储密度等优势日益成为微控制器中重要的程序、数据存储器.然而嵌入式Flash相对较慢的读取速度,制约着微控制器的整体性能,因而提升Flash中指令和数据的读取性能十分重要.为了提升微控制器中嵌入式Flash的读取性能,提出了一种基于缓存和预取的Flash控制器,并对当前缓存和预取的不足进行优化.针对现有缓存适配性差的问题,提出缓存行长自适应技术进行优化.针对传统方式访问组相联缓存时缺失代价和功耗高的问题,提出路命中预测技术进行优化.针对现有预取技术准确性低的问题,提出跨步预取技术进行优化.最后,设计并实现了一款嵌入式Flash控制器,并集成到SoC系统中,搭建了验证平台进行功能仿真和FPGA验证.实验结果表明,采用缓存行长自适应技术后,处理器读取嵌入式Flash的性能得到明显提升(103%);采用路命中预测技术后,处理器读取嵌入式Flash的性能得到进一步提升(2%).采用跨步预取技术后,DMA读取嵌入式Flash的性能得到明显提升(50%).
Embedded Flash has increasingly become an important program and data memory in microcontroller due to its advantages in cost and storage density.However,the relatively slow read speed of embedded Flash restricts the overall performance of the microcontroller,so it is very important to improve the read performance of instruction and data in Flash.In order to improve the read performance of the embedded Flash in the microcontroller,a Flash controller based on cache and prefetch is proposed,and the current cache and prefetch are optimized.in view of the problem of poor adaptability of the existing cache,a cache line size adaptive technology is proposed for optimization.Aiming at the problem of high missing cost and high power consumption when accessing the set-associative cache in the traditional way,a way hit prediction technology is proposed for optimization.Aiming at the problem of low accuracy of the existing prefetching technology,a stride prefetching technology is proposed for optimization.Finally,an embedded Flash controller was designed and implemented,and integrated into the SoC system,and a verification platform was built for functional simulation and FPGA verification.Experimental results show that after adopting the cache line size adaptive technology,the performance of the processor to read embedded Flash is significantly improved(103%);after adopting the way hit prediction technology,the performance of the processor to read embedded Flash is further improved(2%).After adopting stride prefetching technology,the performance of DMA reading embedded Flash has been significantly improved(50%).
作者
杨祎巍
杜俊慧
黄开天
匡晓云
王轲
YANG Yiwei;DU Junhui;HUANG Kaitian;KUANG Xiaoyun;WANG Ke(Electric Power Research Institute of China Southern Power Grid,Guangzhou 510663,Guangdong,China;Guangdong Provincial Key Laboratory of Power System Network Security,Guangzhou 510663,Guangdong,China;College of Information Science and Electronic Engineering,Zhejiang University,Hangzhou 310027,Zhejiang,China;College of Electrical Engineering,Zhejiang University,Hangzhou 310027,Zhejiang,China)
出处
《微电子学与计算机》
2022年第8期107-118,共12页
Microelectronics & Computer
基金
国家重点研发计划资助项目(2018YFB0904900,2018YFB0904902)。