一种具有自适应优化电源抑制比的低静态电流无片外电容LDO

A Low-Quiescent-Current Capacitor-less LDO Using an Adaptive PSR Optimization Technique

为改善无片外电容LDO(Capacitor-Less Low-DropOut regulator,CL-LDO)的电源抑制比(Power Supply Rejection,PSR),本文提出一种低静态电流PSR自适应优化方案.采用push-pull放大器,避免复杂的频率补偿电路与片外大电容,缩小了面积.为优化中频段PSR,在功率管栅极注入一个与频率相关的补偿电流.采用低静态电流的补偿电流动态调整方案,减小压差和负载电流变化对PSR优化效果的影响.该LDO基于0.11μm CMOS工艺,芯片面积为0.026 mm^(2).测试结果表明,在0.1~80 mA负载电流下,静态电流最大值为55μA.在8 kHz到1 MHz频率范围内,在不同压差和负载电流下,PSR最大优化值为21~37 dB.

To improve the power supply rejection ratio(PSR)of capacitor-less low dropout regulator(CL-LDO),this paper proposes an adaptive optimization technique for PSR with low quiescent current.Using push-pull amplifier avoids complex frequency compensation circuits and a bulky external capacitor,thereby reducing the area.To optimize the midband PSR,a frequency-dependent compensation current is injected into the gate of the pass transistor.Moreover,a low power dynamic adjustment scheme of the compensation current is adopted to alleviate the impacts of the dropout voltage and load current variations on the optimal PSR improvement.This LDO was designed and fabricated in a 0.11μm CMOS technology with an active area of 0.026mm^(2).The experimental results show that the maximum quiescent current is 55μA with 0.1-80mA load current.In the frequency range of 8kHz to 1MHz,the maximum PSR improvement is 21-37dB with different dropout voltages and load currents.