基于FPGA的DDR4多通道控制器设计

Design of DDR4 multi-channel controller based on FPGA

在网络通信和图像处理等系统中存在多个子系统同时访问外部存储器的情况,多通道存储控制器则可以有效地解决这个问题。然而随着数据量的激增和处理单元性能的提升,传统的多通道控制器带宽利用率低,难以满足系统对存储器高速存取的要求。因此,针对上述问题,本文设计了基于FPGA的DDR4多通道控制器。该控制器定义了简化的用户接口并支持网络通信中的循环缓冲区设置,降低了使用的复杂度,同时提高了设计的通用性。设计采用基于循环优先级仲裁器的系统转换结构,高效地解决多通道访问冲突问题,提升了系统的带宽利用率。此外,系统采用分片机制实现循环缓冲区内的访问回绕。基于Xilinx KCU116 FPGA的板级测试表明,本文所设计的多通道访问结构的测试结果与仿真一致。在访问长度为4 069字节时,系统最高有效带宽为78.3 Gbps,带宽利用率达到94.0%。

In network communication system, image processing system, and so on, multiple subsystems would access external memory simultaneously. Multi-channel memory controller can solve this problem effectively. With the increasement of data and the improvement of processing unit performance, traditional multi-channel controllers can not meet the requirement of high-speed memory access for system because of low bandwidth utilization. To solve the aforementioned problems, we propose a new kind of DDR4 multi-channel controller on the FPGA in this paper. The controller is defined by simplified user interface and supports ring buffer in network communication, which reduces the use complexity and improves the universality. Multi-channel access conflicts can be solved efficiently by adopting circular priority arbiter. Meanwhile, the bandwidth utilization of the system has been improved. Besides, the rewinding access to the ring buffer is realized by a sharding mechanism. The simulation results are consistent with that on Xilinx KCU116 FPGA. When testing 4 096 MB records, the maximum effective bandwidth of the system is 78.3 Gbps, and the bandwidth utilization rate reaches 94.0%.