一种加速大规模模拟和射频IC后仿真的验证流程

A verification flow on speed-up large-scale analog and RFIC post-layout simulations

近年来,模拟射频IC的功能越来越多,导致片上集成的功能模块快速增加。且进入到先进工艺节点后,单一模块的后仿真网表规模急剧增加。对后仿真速度以及debug效率提出了极高的要求,除了使用更为先进的FULL-SPICE仿真器(比如Cadence Spectre X等)提升仿真速度之外,对后仿真输入文件格式的选择与优化同样是一种有效提升整体后仿真效率的方法。主要讨论Cadence Quantus最新的SmartView输出格式以及与ADE Assembler和Spectre X联合加速后仿真验证的一种新流程,并给出了与传统流程的对比结果。

Recently,the functions and features implemented on Analog/RF ICs increases greatly which requires much more circuit blocks to be integrated into one single chip.On the other hand,with advanced node processes adopted,the post-layout netlist size of a single circuit block increases sharply.All of these pose a high demand on performance and efficiency of post-layout simulations and debugs.Except on adopt advanced Full-SPICE simulators,like Cadence Spectre X,to speed-up post-layout simulations,the choice and optimization method on post-layout input for simulator is another efficient methodology to speed-up overall post-layout verifications.This paper mainly focused on introducing a new post-layout simulation speed-up flow provided by Cadence Quantus SmartView and ADE Assembler with Spectre X,also comparisons with traditional flows are presented.