基于HITOC DK与3DIC Integrity的3DIC芯片物理设计

3DIC physical design of chips based on HITOC DK and 3DIC Integrity technology

使用了Cadence 3DIC Integrity工具,并结合芯盟特有的HITOC(Heterogeneous Integration Technology On Chip)Design Kit,进行了3DIC(3D异构集成)逻辑堆叠逻辑类型芯片的后端实现。项目中对于Cadence 3DIC Integrity工具中的proto seeds(即最小分布单元)进行了拆分、分布、定义等方面的研究优化;并且对于顶层电源规划与Hybrid Bonding bump间的布线排列进行了算法优化,在不影响电源网络强壮性的情况下尽可能多地获得Hybrid Bonding bump数量,从而增加了top die与bottom die间的端口数。最终结果显示,在与传统2D芯片实现的PPA(性能、功耗、面积)对比中,本实验获得了频率提升12%、面积减少11.2%、功耗减少2.5%的收益。

In this paper,Cadence 3DIC Integrity and ICLEAGUE HITOC Design Kit are used to implement the back-end of 3DIC logic stack logic chip.In the project,the separation,distribution,definition and other aspects of proto seeds(i.e.,minimum distribution unit)in Cadence 3DIC Integrity were studied and optimized.In addition,the paper provided an algorithm of routing arrangement between the top-level power planning and Hybrid Bonding bump,which is optimized to obtain as many Hybrid Bonding bumps as possible and also keep the strength of the power network,thus increasing the number of ports between top die and bottom die.The final results of this paper show that compared with PPA(performance,power consumption and area)implemented by traditional 2D chips,the experiment has achieved 12%increase in frequency,11.2%reduction in area and 2.5%reduction in power consumption.