基于薄外延的ESD结构设计

ESD Structure Design Based on Thin Epitaxy

采用薄外延圆片能有效提升抗辐射芯片的抗单粒子闩锁能力,但实测发现栅极接地MOS(GGMOS)结构在薄外延圆片下静电放电(ESD)性能衰减明显。对其衰减机理进行分析,设计了电源钳位ESD结构,对其进行了完整的ESD性能仿真,分析并优化了芯片ESD保护网络,实测结果表明ESD性能满足4kV设计需求。

Thin epitaxial wafer can effectively improve the single event latch-up resistance of radiation-hard chip,but the measured results show that the electrostatic discharge(ESD)performance of the gate grounded MOS(GGMOS)structure is obviously attenuated under the thin epitaxial wafer.The attenuation mechanism is analyzed,and the power clamp ESD structure is designed.The complete ESD performance is simulated,and the whole chip ESD protection network is analyzed and optimized.The measured results show that the ESD performance meets the 4 kV design requirement.