Chiplet接口IP 3DIC混合信号仿真验证

Chiplet interface IP 3DIC mixed signal simulation verification

随着半导体工艺节点向7nm、5nm、甚至3nm等先进工艺演进,大芯片的成本在不断增加,这意味着用先进的工艺节点制造大型SOC芯片正在削弱其经济效益。为了突破这一瓶颈,Chiplet架构应运而生并进入了快速发展期。接口IP与3D封装做为其关键技术,如何保证通过3D封装互联的各接口IP通讯的可靠性成为设计首要考虑因素。本文首先阐述了Chiplet多die互联设计以及顶层验证面临的挑战,接下来详细说明如何使用VCS AMS混合仿真工具来解决当前验证的瓶颈和提升设计效率。

As the semiconductor process node evolves into advanced technologies such as 7nm,5nm and even 3nm,the cost of large chips is increasing.This means that large SOC chips manufactured on advanced process nodes are weaken their economic benefits.To overcome this bottleneck,the Chiplet architecture emerges and enters the fast growth phase.Interface IP and 3D encapsulation are key technologies,and how to ensure the reliability of the IP communication of the interfaces interconnected through 3D encapsulation is the primary design factor.This document first describes the challenges faced by the Chiplet multi-die interconnection design and top-level verification,and then describes how to use the VCS AMS hybrid simulation tool to solve the bottleneck of current verification and improve design efficiency.