An E-band CMOS frequency quadrupler with 1.7-dBm output power and 45-dB fundamental suppression

This paper presents an E-band frequency quadrupler in 40-nm CMOS technology.The circuit employs two push-push frequency doublers and two single-stage neutralized amplifiers.The pseudo-differential class-B biased cascode topo-logy is adopted for the frequency doubler,which improves the reverse isolation and the conversion gain.Neutralization tech-nique is applied to increase the stability and the power gain of the amplifiers simultaneously.The stacked transformers are used for single-ended-to-differential transformation as well as output bandpass filtering.The output bandpass filter enhances the 4th-harmonic output power,while rejecting the undesired harmonics,especially the 2nd harmonic.The core chip is 0.23 mm^(2)in size and consumes 34 mW.The measured 4th harmonic achieves a maximum output power of 1.7 dBm with a peak conversion gain of 3.4 dB at 76 GHz.The fundamental and 2nd-harmonic suppressions of over 45 and 20 dB are achieved for the spectrum from 74 to 82 GHz,respectively.